PATTERN AND POSITION DEPENDENT GATE LEAKAGE AND REDUCTION TECHNIQUE

The leakage power has become a vital downside in modern VLSI technology, with the advent in the area of high performance chips and portable electronics. Thus it is necessarily to invest more time and effort in designing low power chip without sacrificing its high performance. This paper describes a steady state gate leakage based on position and biasing states. As a basic reference universal gates are selected and compared the gate leakage of conventional NAND and NOR gate using 180nm TSMC technology. It is shown that the overall leakage in a NAND -gate is smaller than in a NOR gate if equal size transistors are used. It also compares the leakage value of proposed leakage reduction techniques with conventional NAND gate. Simulation results shows up to 88% in average gate leakage reduction with modified techniques